1. Field of the Invention
This invention relates to a semiconductor device and a method of designing and manufacturing the semiconductor device.
2. Description of the Related Art
Description is made in Japanese Unexamined Patent Application Publication Nos. 2006-024594 and 2007-329237 about a metal-insulator-semiconductor field effect transistor (MISFET) which includes a so-called High-K insulating film made of a material having a high permittivity (High-K) and a gate electrode and a gate wiring which are formed by a metal material on the gate insulating film.
Japanese Unexamined Patent Application Publication No. 2007-329237 points out that, when a CMOS transistor is structured by the above-mentioned MISFET, the threshold voltage of the CMOS transistor cannot be set at a low value, and thus, higher speed and lower power consumption of processing operation of a CMOS logic element can not be accomplished. Accordingly, Japanese Unexamined Patent Application Publication No. 2007-329237 proposes a MIS transistor (so called High-K metal gate (HKMG) transistor) formed of a metal gate having an appropriate threshold voltage and a hafnium-based High-K material.
Japanese Unexamined Patent Application Publication Nos. 2006-024594 and 2007-329237 do not point out a problem which practically arises when MISFETs having different conductivities are arranged adjacent to each other.
Researches by the inventors of this invention revealed that, when a CMOS provided in a peripheral circuit of a DRAM was formed of a MISFET having an HKMG transistor structure, various problems arose.
For the sake of easy understanding of this invention, now, description is made of a problem which arises when a CMOS provided in a peripheral circuit region of a DRAM is formed of an HKMG transistor.
FIG. 24 is a plan view illustrating a peripheral circuit region of a DRAM, and FIG. 25 shows sectional views taken along the line A-A′ of FIG. 24. In FIG. 24, MISFETs having different conductivities are formed in two active regions 21 and 22, respectively, and an element isolation region (STI) 23 defined by two broken lines is formed between the two active regions 21 and 22. A gate wiring BLG connected to gate electrodes of the MISFETs formed in the active regions 21 and 22 is led from the respective active regions. The gate wiring BLG is commonly connected to the MISFETs having different conductivities, and is connected via a contact 25 (FIG. 24) to a conductive layer (not shown) provided above the gate wiring BLG. In the illustrated example, the contact 25 is formed on the STI 23. Further, the gate wiring BLG is connected to gate wirings and gate electrodes (not shown) provided in element formation regions.
Reference is now made to FIG. 25(a). The STI 23 is formed on a semiconductor substrate. An NMOS gate stack (NGS) 26 and a PMOS gate stack (PGS) 27 are provided, which are insulated and separated from each other with the STI 23 interposed therebetween. The NGS 26 is formed of a High-K insulating film, an NMOS metal gate, and polysilicon, while the PGS 27 is formed of a High-K insulating film, a PMOS metal gate, and polysilicon.
In this state, as illustrated in FIG. 25(b), a polysilicon film 28 containing impurities is formed, and further, as illustrated in FIG. 25(c), WSi/WN/W are stacked in this order to form a wiring layer 29, thereby forming the gate wiring BLG. As is clear from FIG. 25(c), a depression 30 is inevitably formed in the gate wiring BLG over the region of the STI 23. Specifically, in a CMOS FET of this kind, when two transistors are connected by the gate wiring BLG, a level difference due to the depression 30 is caused.
In the state illustrated in FIG. 25(c), as illustrated in FIG. 26, an interlayer insulating film 31 of SiN or the like is formed on the gate wiring BLG, and then, the contact 25 is formed at the part of the depression or groove 30. In this case, as illustrated in FIG. 26, there are observed phenomena such as formation of a crevice (seam) in the contact 25 resulting in a contact failure and a defect in which the contact 25 itself pierces the polysilicon 29.